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Memory

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Examination of memory compatibility is a major issue.




Wikipedia - SDRAM Latency Has the following:

SDRAM access has four main measurements (quantified in FSB clock cycles) important in defining the SDRAM latency in a given computer (the 't' prefixes are for 'time'):

tCAS The number of clock cycles needed to access a certain column of data in SDRAM. CAS latency, or simply

CAS, is known as Column Address Strobe time, sometimes referred to as tCL.

tRCD (RAS to CAS Delay) The number of clock cycles needed between a row address strobe (RAS) and a CAS. It is the time required between the computer defining the row and column of the given memory block and the actual read or write to that location. tRCD stands for Row address to Column address Delay time.

tRP (RAS Precharge) The number of clock cycles needed to terminate access to an open row of memory, and open access to the next row. It stands for Row Precharge time.

tRAS (Row Active Time) The minimum number of clock cycles needed to access a certain row of data in RAM between the data request and the precharge command. It's known as active to precharge delay. According to Mushkin, in practice for DDR SDRAM, this should be set to at least tRCD + tCAS + 2 to allow enough time for data to be streamed out. [1]. It stands for Row Address Strobe time.

Wikipedia - DDR3 SDRAM 

M4N68T-M LE V2 Entry-level DDR3 platform with High Quality & Core Unlocker 

nVidia ION 

mydropintheocean 

mydropintheocean 






© Tom de Havas 2011. The information under this section is my own work it may be reproduced without modification but must include this notice.







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